The concept of phase locked loops (PLLs) dates back to the 1930's where it was used in radar synchronization and other communications applications. Today, PLLs are used in satellite communications systems, navigation systems, computers, cellular communication systems, and radio systems in general.
Radio Frequency (RF) synthesizers are commonly utilized substitutes for crystal controlled transmitter/receiver oscillators. A combination of a master oscillator signal with a secondary signal in a suitable phase detector can provide the choice of a number of controlled frequencies. If a variable frequency oscillator is used with a digital frequency synthesis technique, a virtually unlimited number of stable discrete frequencies directly related to the frequency of the master oscillator are available.
A synthesizer generally makes use of a phase-locked loop (PLL) which also includes a voltage controlled oscillator (VCO), a reference oscillator, a loop filter, and a phase detector. In addition, the synthesizer will also include one or more programmable or switchable multipliers or dividers so the loop can be locked to various multiples of the reference source frequency or one of its subharmonics.
A common use for these synthesizers is in the area of communication equipment, such as RF modems and radio communication devices. This area also involves the increasing use of portable or mobile battery powered radio communication equipment, such as cellular type radio-telephone equipment.
One problem which arises is the limited battery power available for the portable hand-held type of units. It has been found that during normal operation, the synthesizer requires substantial power to operate. Portable radios are frequently designed to operate efficiently for an eight-hour duration on some predetermined duty cycle designating the percentage of time which would be used to receive, transmit, and remain on standby. For example, a 5-5-90 would represent a 5% receive, 5% transmit, and 90% standby. As can be seen, such a radio spends the majority of its time in a standby mode.
To address the power problem, some units have been designed with the capability to disconnect the synthesizer, or portions thereof, from the power supply while in standby. This disconnect may be done on a duty cycle basis, requiring the synthesizer to perform many cycles of active/inactive (standby) operation during the equipment's standby mode. However, when these functions are reactivated, the VCO signal must restabilize before it is usable. During reactivation the PLL signal to the VCO can actually cause the VCO signal to drift away from the desired frequency before restabilizing.
To resolve this problem, the prior art has provided various means of inhibiting portions of the synthesizer until the signals are stabilized. However, this results in a delay to suitable operation and possible loss of data.
Therefore, there still exists a need in the industry for a device and method of saving battery power while at the same time avoiding delays in reestablishing a signal lock.